External Memory Protection on FPGA-Based Embedded Systems
A work by: Joćo Carlos Resende ; Aleksandar Ilic and Ricardo Chaves
Contacts:
joaocresende@tecnico.ulisboa.pt
ricardo.chaves@tecnico.ulisboa.pt
Page
created 06/09/2024
Last
Modified 06/09/2024
This
is a web page for support material regarding the publication of the article: External
Memory Protection on FPGA-Based Embedded Systems published on 27th Euromicro Conference Series on Digital System Design (DSD),
August 2024.
In
this work, a memory pipeline bridge between an embedded CPU and external DDR memory
was created on a Zynq-7100 (see Figure below).
The
purpose of this bridge is to provide a testing template for memory access latency
through FPGA, with an adjustable size for the intermedium pipeline.
Figure 1: Overall view of the Memory bridge
Besides
the memory bridge itself, Performance Counters are also included tapping the
AXI4 transmissions on both sizes of the bridge.
These
counters account how many write/read transmissions have been performed and make
a histogram of how many FPGA clock cycles those transmissions took.
Figure 2: Circuit for creating a transmission
histogram by clock cycle
The
following link contains a fully assembled Xilinx Vivado
and Vitis 2020.2 project of the memory bridge, alongside separate source files
(vhdl and C codes) and instructions for assembly from
scratch.